1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly data read and write circuits of a dynamic random access memory (which will also be referred to as a xe2x80x9cDRAMxe2x80x9d hereinafter).
2. Description of the Background Art
A hierarchical data I/O (input/output) line structure and a direct sensing system have been used as techniques for satisfying demands for large capacities and high operation speeds of semiconductor memories in recent years.
With increase in capacity of memories, parasitic capacitances of I/O lines may increase and cause remarkable delay in signal transmission. The hierarchical I/O line structure is employed for reducing an influence of this delay by hierarchically arranged I/O lines. For example, the hierarchical I/O line structure is described, e.g., in xe2x80x9cUltra LSI Memoryxe2x80x9d (Kiyoo ITO, BAIFUKAN), pp. 167-170.
The direct sensing system is a technique having such a feature that the operation speed is increased by directly taking memory cell signals onto I/O lines without waiting for amplification by sense amplifiers, and is disclosed, e.g., in xe2x80x9cUltra LSI Memoryxe2x80x9d (Kiyoo ITO, BAIFUKAN), pp. 165-167.
FIG. 31 schematically shows an I/O line structure of a semiconductor memory device 500 having a typical hierarchical I/O line structure.
Referring to FIG. 31, a memory cell array of a semiconductor memory device 500 is divided into a plurality of sense amplifier blocks 501 of k in number. A sense amplifier S/A amplifies data read onto bit line pair BL and /BL provided correspondingly to a column of memory cells. Sense amplifiers S/A in each sense amplifier block are activated independently of those in other sense amplifier blocks.
The I/O lines provided for transmitting output data are divided into lines I/O1-I/O3 which are hierarchically arranged for reducing an influence of delay in data transmission caused by increase in parasitic capacitance. Further, main amplifiers MA1 and MA2 are arranged for amplifying potential differences occurring on I/O lines I/O2 and I/O3, respectively.
According to the above structure, a column decoder/driver 502 controls a column select signal, and thereby the sense amplifier amplifies the data on the bit line pair of the corresponding column and transmits the same onto the data I/O line. In general, it is I/O1 in which increase in parasitic capacitance may cause a problem. Therefore, I/O1 is divided, and data lines I/O2 crossing I/O1 are connected to divided I/O1 with switches therebetween, respectively.
Further, upper or high-order data lines I/O3 connected to the plurality of lines I/O2 are arranged. Thereby, the device can perform fast input/output of a large quantity of data as a whole. In particular, lines I/O2 can have a simple structure, and therefore can be arranged on the memory cell array so that lines I/O2 do not significantly increase a chip area.
According to the above system, however, many switches controlling connection between the I/O lines are required, resulting in disadvantageous increase in chip area.
FIG. 32 conceptually shows a semiconductor memory device employing a typical direct sensing system, and particularly a structure of a column select circuit 510 relating to read and write of data.
Referring to FIG. 32, word line WL and a bit line pair BL and /BL are arranged correspondingly to a memory cell MC. Column select circuit 510 includes sense amplifier S/A for amplifying data on the bit line pair, a read select circuit 511 for reading data from the memory cell, a write select circuit 512 for writing data into the memory cell, a read data line pair RO and /RO and a write data line pair WI and /WI.
When word line WL is activated, the data in memory cell is read onto bit line pair BL and /BL, and is amplified by sense amplifier S/A activated by sense amplifier activating signals xcfx86N and /xcfx86p. A read gate transistor 513 or 514 included in read select circuit 511 is turned on by the data read onto bit line pair BL and /BL, and directly drives data read line pair RO and /RO in accordance with selection by a read column select signal YR. Thereby, a voltage difference occurring on read data line pair RO and /RO is amplified and taken out. In this manner, the data stored in the memory cell can be read out.
Data writing is performed by writing the data, which is transmitted onto write data line pair WI and /WI, onto bit line pair BL and /BL in accordance with selection by a write column select signal YW.
As described above, the direct sensing system increases the speed of data read operation by directly driving the read data line pair based on the memory cell signal read onto the bit line pair.
Although the speed of data read operation can be increased, disadvantageous increase in number of circuit elements and increase in layout area occur because the column selection in the read operation is performed independently of that in the write operation, and additional read gate transistors are required.
For improving production yields while increasing capacities of memories, such a structure is employed that a memory cell array includes a preliminary memory cell array having a spare line (a spare row or a spare column) for each unit of rows or columns, and a failed memory cell having a defect is repaired by replacing the row or column containing the failed memory cell with the spare line. Thus, a so-called redundant repair structure is employed.
FIG. 33 conceptually shows a structure of a redundant repair circuit 520 in the redundant repair structure.
Referring to FIG. 33, redundant repair circuit 520 includes a spare memory cell array 521 in which spare rows or columns are arranged, and program elements 525a and 525b which are arranged correspondingly to the spare row and spare columns, respectively.
Each of program element 525a and 525b is formed of a program fuse which can be blown by laser applied thereto, or a thin insulating film to be broken by a high voltage for turning on the element.
For example, when a defect occurs in a memory cell at (x1, y1), i.e., a row address x1 and a column address y1 in a regular memory cell array, processing is externally effected on the program element for replacing the whole regular row at row address x1 with one spare row. Naturally, processing may be performed to use the spare column based on column address y1.
When the address of row or column containing the defective memory cell is determined, the redundant repair structure can repair a defect in the regular memory cell by replacement with the spare row or column of the spare memory cells based on the state of program elements in the above manner. Thereby, the redundant repair structure can reduce a product rejection rate of semiconductor memory devices.
In the conventional redundant repair structure, however, the program elements are provided for both the rows and columns of the preliminary memory cell lines. Therefore, the chip having a huge capacity requires a significantly large chip area due to increase in number of the program elements.
Since transistors forming the memory cells have been scaled down in accordance with increase in capacity, increase in number of the transistors does not cause a significant problem in the area of the preliminary memory cell array. However, the program elements such as fuse elements are less scaled down compared with the memory cells. Accordingly, increase in number of the program elements significantly increases the layout area.
An object of the invention is to provide a semiconductor memory device capable of suppressing increase in layout area, which may be cause by employing the direct sensing system and the hierarchical I/O line structure for increasing the capacity and operation speed.
In summary, the present invention is a semiconductor memory device for reading and writing storage data in accordance with an address signal and including a plurality of memory cell blocks, read column select lines, column select circuits and read data transmitting circuits.
The plurality of memory cell blocks are arranged in a matrix of a first number of columns and a second number of rows, and each include a plurality of memory cells arranged in a matrix of rows and columns, bit line pairs arranged corresponding to the memory cell columns, respectively, and at least one first data I/O line pair for transmitting a read data from one of the memory cells selected according to an address signal.
The read column select lines instruct selection of at least one of the memory cell columns.
The column select circuit selectively activates at least one of the read column select lines in accordance with the address signal.
The read data transmitting circuits are provided corresponding to the memory cell blocks, respectively for transmitting the read data sent from the selected memory cell column onto the first data I/O line pair. Each read data transmitting circuit includes a plurality of first gate circuits provided corresponding to the memory cell columns, respectively, and being activated by the corresponding one among the read column select lines, and each of the first gate circuits has a first read gate switch for connecting the corresponding read column select line to one line of the first data I/O line pair in accordance with the potential level on one line of the bit line pair, and a second read gate switch for connecting the corresponding read column select line to the other line of the paired first data I/O line pair in accordance with the potential level on the other line of the bit line pair.
According to another aspect of the invention, a semiconductor memory device for reading and writing the storage data in accordance with an address signal, includes a plurality of memory cell blocks, a plurality of read column select lines, column select circuits, global data I/O line pairs, read data transmitting circuits and a column select line switching circuit.
The plurality of memory cell blocks are arranged in a matrix of a first number of columns and a second number of rows, and each including a plurality of memory cells arranged in a matrix of rows and columns, bit line pairs arranged corresponding to the memory cell columns, respectively, and at least one first data I/O line pair transmitting a read data read from one of the memory cells.
The plurality of read column select lines instruct selection of one of the memory cell columns.
The column select circuits are provided corresponding to the memory cell blocks, respectively, and selectively activates at least one read column selects line in accordance with the address signal.
The global data I/O line pairs are provided in common for the second plurality of the memory cell blocks belonging to the identical column of the memory cell blocks, and are connected to the first data I/O line pairs of the second plurality of the memory cell blocks.
The read data transmitting circuits transmit the read data from the selected memory cell column onto the global data I/O line pair, and are provided corresponding to the memory cell blocks, respectively. Each of read data transmitting circuits includes a third number of fourth gate circuits each provided for each of the memory cell columns in each of the memory cell blocks, each of fourth gate circuits being activated by a corresponding one of the read column select lines. The fourth gate circuits each have a fifth read gate switch for connecting the corresponding read column select line to a first one out of the remainder of the read column select lines in accordance with the potential level on one line of the bit line pair, and a sixth read gate switch for connecting the corresponding read column select line to a second one out of the remainder of the read column select lines in accordance with the potential level on the other line of the bit line pair and a plurality of column select line switching circuits each for connecting the first and second read column select lines to the lines of said global data I/O line pair, respectively, in accordance with an instruction from a corresponding one of the column select circuits.
According to still another aspect of the invention, the invention provides a semiconductor memory device for reading and writing storage data in accordance with an address signal, including a regular memory cell array and a redundant repair circuit.
The regular memory cell array has a plurality of regular memory cells arranged in rows and columns, and is divided into a plurality of regular memory cell groups each having at least one memory cell row and at least one memory cell column having, a correspondence established in advance with each other.
The redundant repair circuit is provided for repairing a regular memory cell having a defect, and includes a plurality of spare memory cell groups, a plurality of replacement address storing circuits and an address comparing circuit.
The plurality of spare memory cell groups are replaced with the regular memory cell groups when the address signal matches with a replacement address.
Each of the spare memory cell groups includes spare memory cell rows and spare memory cell columns being equal in number to the memory cell rows and the memory cell columns of each of the regular memory cell groups, respectively.
The plurality of replacement address storage circuits are provided for the spare memory cell groups, and store, as the replacement addresses, the addresses corresponding to the regular memory cell groups containing the defective memory cells, respectively.
The address comparing circuit instructs repairing of the regular memory cell in accordance with the comparison between the address signal and the replacement address.
Accordingly, the invention can achieve the following major advantage. Since the read operation based on the direct sensing method can be executed by the column select gates formed of a reduced number of circuit elements, the direct sensing method and the hierarchical I/O line structure can be employed for increasing the capacity and the operation speed while suppressing increase in the layout area.
Since the column select line can be used also as the data I/O line, lines can be reduced in number, and therefore the layout area can be further reduced.
Moreover, the replacement address storing circuits are arranged to have a correspondence with both the row addresses and the column addresses for storing the address of the defective memory cell. Therefore, the replacement address storing circuits can be reduced in number while maintaining the redundant repair performance, and the defective memory cell can be repaired with a reduced layout area.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.